One embodiment of the present invention relates to a method and also an apparatus for measuring a surface profile of a sample which contains processed semiconductor material, that is, a semiconductor wafer or a part of a semiconductor wafer.
In the production of semiconductor components such as, for example, DRAM memory modules (“Dynamic Random Access Memory”), logic circuits, optoelectronic components or MEMS (“Micro-Electro-Mechanical Systems”), the associated integrated circuits are firstly processed at the wafer level. After the fabrication steps have ended, the wafer is singulated into chips each containing the corresponding circuits and they are packaged in suitable housings in order to produce the semiconductor components.
In order to produce DRAM memory modules, the wafer undergoes for example a multiplicity of patterning steps in the course of which, inter alia, layers are deposited and, in particular, depressions are etched into the substrate surface.
FIG. 7A illustrates an exemplary cross-sectional view through a trench capacitor associated with a DRAM memory cell after the so-called recess 2 etching step has been carried out.
In FIG. 7A, an Si3N4 layer 10 is deposited on the surface of a silicon wafer 1. Capacitor trenches 11 are etched into the resulting surface 3, at the edge of which capacitor trenches, in each case after the formation of a bottom capacitor electrode (not shown) a capacitor dielectric (not shown) and a top capacitor electrode 15, an SiO2 spacer 12 is respectively formed, which acts as an insulation collar in the finished storage capacitor. The resulting trench is filled with a polysilicon filling 13 and etched back in the recess 2 etching step for preparing the contact regions for connecting the storage capacitor to the selection transistor, thus resulting in the depression 14 having the depth R2 with the trench width d as illustrated in FIG. 7A.
Metrology methods are of particular significance for further development of existing processes and products. They are used, for example after carrying out the recess 2 etching step, to check whether the etched depression has the predefined depth and width and whether the bottom has been etched flat or has bulges. Furthermore, contaminants that occur, for example regions removed incompletely during etching, can be demonstrated by means of metrology methods. The insights obtained by means of the metrology methods serve on the one hand for monitoring the individual process steps in order to ensure that the processed structures satisfy the necessary requirements, and on the other hand for process optimization. For example, on the basis of the insights obtained, the etching parameters are altered for wafers that are subsequently to be processed.
Metrology methods that are customary at the present time include in particular atomic force microscopy and other scanning probe methods and physical defect analysis, including scanning electron microscopy or FIB methods (“Focused Ion Beam”). Although the methods of physical defect analysis do indeed yield an actual image or profile of the structures produced, they have the disadvantages. For example, the wafer has to be destroyed for carrying out examination methods of this type, as a result of which practical applicability is restricted.
Examples of further customary measurement methods are IRSE (Spectroscopic Ellipsometry using InfraRed beams) and scattering methods (Spectroscopic Scatterometry or Specular Spectroscopic Scatterometry). Although the IRSE methods enable the depth to be determined in vertical structures, the measurement of profiles is not possible. Scattering methods enable profiles to be reliably reconstructed as long as the structures retain their periodic arrangement and they have a simple construction.
When using the measurement methods mentioned, moreover, the problem also occurs that the patterned zones contain different types of materials with different properties. Thus, when examining the trenches illustrated in FIG. 7A, the respective properties of the insulator layers 10, 12 and of the polysilicon fillings 13, 15 influence the measurement result and also have to be taken into account in the modeling—when using scattering methods for example.
In order to increase the storage capacity of DRAM memory cells, it is necessary to introduce ever smaller feature sizes and for example to etch depressions ever deeper. This means that in FIG. 7A by way of example, the trench width d becomes smaller and smaller, and the depth R2 and the aspect ratio, that is to say the ratio of trench depth to trench width, greatly increases.
The construction of capacitor trenches, by way of example, also increases in complexity since structures are formed on one side within the trenches.
This is illustrated by way of example in FIG. 7B. In FIG. 7B, a structure 16 made of SiO2, for example, is formed on one side within a capacitor trench 11 partly filled with a polysilicon material 13. The width d of the capacitor trench 11 is 90 nm for example, and the width of the structure 16 is 50 nm, so that the lower trench region has a width b of 40 nm. The depth R of the trench 11 is 380 nm, for example.
If the metrology methods that are customary at the present time are applied to the structures of this type, then various problems occur. For example, it becomes difficult, on account of the evaluation algorithms of the atomic force microscope, to measure trenches having a width d of less than 70 nm. Furthermore, the tip form of the probe and also the scanning mechanism used corrupt the measurement result. Moreover, it is impossible for such a narrow gap as that illustrated in FIG. 7B to be scanned using atomic force microscope probes that are customary at the present time.
A particular problem arises if, for example, a structure as illustrated in FIG. 7C is to be measured. In FIG. 7C, a one-sided structure 16, for example made Of SiO2, is formed in an upper part of a trench 11 formed in a semiconductor substrate 1 in such a way that the resulting trench diameter in a lower trench part is larger than in an upper trench part. As a consequence it is impossible to measure the lower trench part of this structure using an atomic force microscope, for example, since the part lying below the structure 16 is not accessible to the probe of the atomic force microscope.
U.S. Pat. No. 5,772,905 describes a lithographic method for transferring a structure, in the case of which a shaped piece with nanostructures in its surface region is impressed into a resist layer on a substrate. The pattern defined on the shaped piece is transferred into the resist layer by exerting pressure and heating the resist layer to a temperature above the glass transition temperature for a predetermined time duration and then allowing it to cool down. The structure of the shaped piece is transferred into the substrate surface by means of a suitable aftertreatment using, by way of example, reactive ion etching and, if appropriate, a subsequent deposition method followed by lift-off.
U.S. Pat. No. 6,334,960 B1 describes a further lithographic method for transferring a structure from a shaped piece to a semiconductor wafer, in the case of which the semiconductor wafer is covered with a polymer transfer layer and a polymerizable liquid. The shaped piece is brought into contact with the polymerizable liquid, and the polymerizable liquid is cured by radiating in UV light.